#c_lang #radio #rpi #fpga #pi #software #sdr #raspberry #icestorm #rf #yosys #ice40 #defined
https://github.com/cariboulabs/cariboulite
https://github.com/cariboulabs/cariboulite
GitHub
GitHub - cariboulabs/cariboulite: CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR - cariboulabs/cariboulite
#assembly #cpu #fpga #riscv #soc #softcore #spinalhdl #verilog #vhdl
This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.
Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.
https://github.com/SpinalHDL/VexRiscv
This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.
Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.
https://github.com/SpinalHDL/VexRiscv
GitHub
GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation
A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.
#verilog #cocotb #embedded #fpga #iss #risc_v #rtl #verilator #verilog #vpn #vproc #wireguard
This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments.
https://github.com/chili-chips-ba/wireguard-fpga
This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments.
https://github.com/chili-chips-ba/wireguard-fpga
GitHub
GitHub - chili-chips-ba/wireguard-fpga: Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7…
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d...
1❤3
#cplusplus #arm #baidu #deep_learning #embedded #fpga #mali #mdl #mobile #mobile_deep_learning #neural_network
Paddle Lite is a lightweight, high-performance deep learning inference framework designed to run AI models efficiently on mobile, embedded, and edge devices. It supports multiple platforms like Android, iOS, Linux, Windows, and macOS, and languages including C++, Java, and Python. You can easily convert models from other frameworks to PaddlePaddle format, optimize them for faster and smaller deployment, and run them with ready-made examples. This helps you deploy AI applications quickly on various devices with low memory use and fast speed, making it ideal for real-time, resource-limited environments. It also supports many hardware accelerators for better performance.
https://github.com/PaddlePaddle/Paddle-Lite
Paddle Lite is a lightweight, high-performance deep learning inference framework designed to run AI models efficiently on mobile, embedded, and edge devices. It supports multiple platforms like Android, iOS, Linux, Windows, and macOS, and languages including C++, Java, and Python. You can easily convert models from other frameworks to PaddlePaddle format, optimize them for faster and smaller deployment, and run them with ready-made examples. This helps you deploy AI applications quickly on various devices with low memory use and fast speed, making it ideal for real-time, resource-limited environments. It also supports many hardware accelerators for better performance.
https://github.com/PaddlePaddle/Paddle-Lite
GitHub
GitHub - PaddlePaddle/Paddle-Lite: PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎)
PaddlePaddle High Performance Deep Learning Inference Engine for Mobile and Edge (飞桨高性能深度学习端侧推理引擎) - PaddlePaddle/Paddle-Lite