#assembly #cpu #fpga #riscv #soc #softcore #spinalhdl #verilog #vhdl
This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.
Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.
https://github.com/SpinalHDL/VexRiscv
This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.
Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.
https://github.com/SpinalHDL/VexRiscv
GitHub
GitHub - SpinalHDL/VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation
A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.