#verilog

https://github.com/nvdla/hw

#verilog

https://github.com/darklife/darkriscv

#verilog

https://github.com/pwmarcz/fpga-chip8

#verilog

https://github.com/T-head-Semi/wujian100_open

#verilog

https://github.com/schlae/graphics-gremlin

#assembly #cpu #fpga #riscv #soc #softcore #spinalhdl #verilog #vhdl

This repository provides a highly configurable RISC-V CPU implementation written in SpinalHDL. Here are the key benefits and features The CPU can be customized with various plugins to add or remove features such as instruction and data caches, multiplication and division units, floating-point units, and more.
- **Performance** It includes a debug module that allows for Eclipse debugging via GDB, OpenOCD, and JTAG connections.
- **Compatibility** The CPU can be optimized for different FPGA targets, and it does not use any vendor-specific IP blocks.
- **Extensibility**: New instructions and peripherals can be added easily through the plugin system, making it highly extensible.

Overall, this implementation offers a flexible and powerful RISC-V CPU solution that can be tailored to various needs and applications.

https://github.com/SpinalHDL/VexRiscv

#verilog #cocotb #embedded #fpga #iss #risc_v #rtl #verilator #verilog #vpn #vproc #wireguard

This project creates an open-source, hardware-based WireGuard VPN using an affordable FPGA board, making fast and secure VPNs more accessible. Unlike slow software VPNs or costly proprietary hardware, this FPGA design runs WireGuard encryption and packet processing at near wire speed without needing a PC host. It uses common tools and languages (SystemVerilog, open-source FPGA tools) and includes a soft CPU for control tasks and hardware logic for data encryption and routing. This means you get a faster, more efficient, and customizable VPN solution that is open and affordable, ideal for learning, development, or deployment in cost-sensitive environments.

https://github.com/chili-chips-ba/wireguard-fpga